Over the last few decades, the electronics industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices. The most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applicability and numerous disciplines. One such silicon-based semiconductor device is a metal-oxide-semiconductor (MOS) transistor.
The principal elements of a typical MOS semiconductor device are illustrated in FIG. 1. The device generally includes a gate electrode 101 (which is typically formed of polysilicon) which acts as a conductor and to which an input signal is typically applied via a gate terminal (not shown). Heavily doped source 103 and drain 105 regions are formed in a semiconductor substrate 107 and are respectively connected to source and drain terminals (not shown). A channel region 109 is formed in the semiconductor substrate 107 beneath the gate electrode 101 and separates the source 103 and drain 105 regions. The channel is typically lightly doped with a doping type opposite to that of the source 103 and drain 105 regions. The gate electrode 101 is physically separated from the semiconductor substrate 107 by an insulating layer 111, typically an oxide layer such as SiO.sub.2. The insulating layer 111 is provided to prevent current from flowing between the gate electrode 101 and the semiconductor source region 103, drain region 105 or channel region 109.
In operation, an output voltage is typically developed between the source and drain terminals. When an input voltage is applied to the gate electrode 101, a transverse electric field is set up in the channel region 109. By varying the transverse electric field, it is possible to modulate the conductance of the channel region 109 between the source region 103 and drain region 105. In this manner an electric field controls the current flow through the channel region 109. The current flow through the channel region is typically referred to as the source-drain current. This type of device is commonly referred to as a MOS field-effect-transistors (MOSFET).
Semiconductor devices, like the one described above, are used in large numbers to construct most modern electronic devices. As a larger number of such devices are integrated into a single silicon wafer, improved performance and capabilities of electronic devices can be achieved. In order to increase the number of semiconductor devices which may be formed on a given surface area of a substrate, the semiconductor devices must be scaled down (i.e., made smaller). This is accomplished by reducing the lateral dimensions of the device structure. As the device structure dimensions are reduced laterally, it also becomes necessary to scale down the vertical dimensions of the device.
Gate electrodes and the spacing between adjacent gate electrodes are important features which must be scaled down as the device structure is made smaller. Gate electrodes are typically formed by forming a layer of polysilicon over the substrate, masking the polysilicon layer, and removing unmasked portions of the polysilicon layer to form polysilicon lines. This is typically performed using well-known deposition and photolithography techniques. Each polysilicon line ("poly line") typically functions as one or more gate electrodes.
As the device structure is scaled down, the spacing between adjacent poly lines is decreased. Control over the characteristics of the poly lines and their associated transistors is reduced. For example, when etching closely spaced poly lines the resultant or actual width of the poly lines is typically smaller than the width specified by design specifications ("design width"). The differences between the design width and actual width of the poly lines can dramatically impact device performance. For example, electrical properties, such as drive currents, of the transistors associated with closely spaced poly lines can vary from design specifications.
The differences in poly line width is of significant concern in devices where adjacent poly lines are so densely packed that the electrical properties of the transistors associated with the dense poly lines cannot be measured directly. In these instances, the change in the electrical properties of the transistors cannot be taken into account during transistor design.